1. Field of the Invention
This invention relates to phase-locked loop circuits and more particularly to charge-pump phase locked loop circuits.
2. Description of the Relevant Art
As semiconductor processing technology advances, chip performance improves in two ways. One improvement is the number of functional elements integrated onto a single die, and the other is the speed of operation of the circuits. When the speed of operation is increased to enhance the computational power of a chip, accurate clock generation must typically be provided to accommodate synchronous communication protocol. Phase locked loop circuits are a common source for such clock signal generation.
Charge-pump phase locked loop circuits are known for extremely accurate phase tracking capability. During operation, an edge of an internal clock within the charge-pump phase locked loop is accurately aligned to an edge of an external clock by directly comparing the two phases with a sequential phase-frequency detector. Depending upon the phase difference, a capacitive element within the phase locked loop is either charged or discharged. The voltage level across this capacitive element is thereby used to control the phase of the internal clock.
However, there are several problems associated with charge-pump phase locked loop circuits. The first problem relates to an interrelationship between bandwidth and noise jitter (phase jitter). In general, both a high bandwidth and a low noise jitter are desirable. A high bandwidth usually assures a fast locking time characteristic, While low noise jitter assures extremely accurate phase alignment after locking to an input signal frequency. In the design of a typical charge pump phase locked loop circuit, when the bandwidth is increased, an undesirable increase in noise jitter also results. Therefore, a designer must consider the trade-offs between high bandwidth and low noise jitter when designing a phase locked loop circuit for a particular application.
There are several other problems associated with charge-pump phase locked loop circuits. To avoid the possibility of false locking to a sub-harmonic frequency, a phase locked loop circuit is typically designed with a relatively small dynamic range. Thus, the range of frequencies to which the phase locked loop can lock is limited. Other problems within phase locked loop circuits can occur as a result of poor common mode noise rejection, power supply noise rejection and other types of internal noise rejection.